Synchronization Register Chain Length logic option
Allows you to specify the retiming behavior for a sequence of synchronization or metastability registers. All registers in the sequence have the same clock and have no fan-out in between, such that the first register is fed by a pin or by logic in another clock domain. These registers are not moved during gate-level retiming. The length of the sequence is specified by a variable.
This option is available for all Intel devices that the Intel® Quartus® Prime software supports.
Scripting Information |
Keyword: synchronization_register_chain_length Settings: 2 | <register value> *default |
Note: For more information about metastability, see
the "Managing Metastability with the Intel® Quartus® Prime Software" chapter
in the Intel® Quartus® Prime Handbook, volume 1.