lpm_decode Intel FPGA IP

Parent topic: lpm_decode Intel FPGA IP

Resource Usage

Uses one logic cell per output for up to 16 outputs, and two logic cells per output for more than 16 outputs.

Parent topic: lpm_decode Intel FPGA IP

Contact Intel | Terms of Use | Trademarks | Privacy | Send Feedback

Copyright© Intel Corporation. All rights reserved. INTEL, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Intel Corporation in the U.S. and other countries.