EDA Netlist Writer Reports

EDA Netlist Writer Summary Report:

Summarizes the following information about the compilation:

  • EDA Netlist Writer Status shows the status, end date, and end time of the EDA Netlist Writer operation.
  • Revision Name shows the revision name specified in the Revisions dialog box (Project menu).
  • Top-level Entity Name
  • Family shows the device family name specified in the Device dialog box of the Settings dialog box.

EDA Netlist Writer Simulation Reports:

Simulation Settings Report

Reports the simulation settings you specified in theSettingsdialog box (Assignments menu).

  • Tool Name shows the name of the Third Party EDA tool and HDL design file type you specified.
  • Time scale shows the time scale you specified for this compilation.
  • Truncate long hierarchy paths shows the setting you specified for the Truncate long hierarchy paths option.
  • Map illegal HDL characters shows the setting you specified for the Map illegal HDL characters option.
  • Flatten buses into individual nodes, shows the setting you specified for the Flatten buses into individual nodes option.
  • Maintain hierarchy, shows the setting you specified for the Maintain hierarchy option.
  • Bring out device-wide set/reset signals as ports, shows the setting you specified for the Bring out device-wide set/reset signals as ports option.
  • Enable glitch filtering shows the setting you specified for the Enable glitch filtering option.
  • Generate Power Estimate Scripts shows the option you specified in the Generate Value Change Dump file scriptoption.
  • Test Bench design instance nameshows the test bench design instance name you specified when you created anew test benchfile.
  • Do not write top level VHDL entity shows the setting you specified for the Do not write top level VHDL entity option.
  • Disable setup and hold time violations detection in input registers of bidirectional pins shows the setting you specified for the Disable setup and hold time violations detection in input registers of bidirectional pins option.
  • Architecture name in VHDL output netlist shows the name you specified in the Architecture name in VHDL output netlist option.

Generated Files Report

Lists files generated by the EDA Netlist Writer for use with Simulation tools.

EDA Netlist Writer Formal Verification Tools Rports:

Reports the name of the Formal Verification tool specified in the Settings dialog box (Assignments menu).

EDA Netlist Writer Board-Level Tools Reports:

Board-Level Settings Report

Lists the Board Symbol Format, Board Signal Integrity Format, and Board Timing Analysis Format tools specified in the Settings dialog box (Assignments menu).

Generated Files Report

Lists files generated by the EDA Netlist Writer for use with board-level tools. Separate lists are presented for Board Symbol, Board Signal Integrity, and Board Timing Analysis files.

EDA Netlist Writer Messages:

Reports messages generated by the EDA Netlist Writer during the current compilation. The EDA Netlist Writer generates info, warning, and error messages that report conditions observed during the EDA Netlist Writer process.

You can right-click a message in the EDA Netlist Writer Messages report and click Help to display help on the selected message, or click Locate to view a list of options available for the selected message.