ID:13284 Verilog HDL or VHDL arithmetic warning at <location>: loss of carry in addition or borrow in subtraction

CAUSE: In a Verilog Design File (.v) or a VHDL Design File (.vhd), you used an addition or subtraction operator to add or subtract two values. However, the size of the result was too small to store the carry or borrow bit.

ACTION: If losing the carry or borrow does not affect the design functionality, you may ignore this message. Otherwise, increase the size of the operands for addition or subtraction so that the size of the intermediate result is wide enough to store the carry or borrow.