ID:276026 Inferred RAM node "<name>" from synchronous design logic. The RAM node maps into an M-RAM that powers up into an unknown state

CAUSE: You specified a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that act as RAM. Analysis & Synthesis replaces the registers with the specified RAM node. Later on, this node will infer an altsyncram megafunction to implement the registers with an M-RAM. However, the M-RAM powers up into an unknown state that shows an undefined value if you read from a memory address before writing to it.

ACTION: If you intend Analysis & Synthesis to replace the registers with an M-RAM that is not dependent on the initial contents, no action is required. Avoid this message by replacing the registers and address logic with an explicit instantiation of an altsyncram megafunction. If you require an initialized RAM, change your design to specify the power-up state of the registers that comprise the RAM, or use the ramstyle synthesis attribute to map the RAM into a memory block that initializes to a known state. For example, M512 memory blocks and M4K memory blocks initialize to GND. Finally, if you do not want a RAM, turn off the Auto RAM Replacement logic option.