ID:176584 Output pin "<name>" (external output clock of PLL "<name>") uses I/O standard <name>, has current strength <name>, output load <number>pF, and output clock frequency of <name>, but target device can support only maximum output clock frequency of <name> for this combination of I/O standard, current strength and load

CAUSE: You specified the output clock frequency, I/O standard, current strength and load for the specified output pin, which is an external output clock of the specified PLL. However, the output clock frequency is higher than the maximum output clock frequency that the target device can support for the specified combination of I/O standard, current strength and load.

ACTION: Lower the output clock frequency, current strength or load so that the output frequency of the PLL is less than the maximum frequency.