ID:15043 Input port inclk[<number>] of PLL "<name>" and its source clk[<number>] (the output port of PLL "<name>") have different specified frequencies, <number> and <number> respectively

CAUSE: The input clock frequency of the specified PLL at the specified port differs from the output clock frequency of the source PLL at the corresponding output port.

ACTION: Change the frequencies of the specified input and output clocks so they match.