ID:15040 Output clock clk[<number>], which is the compensated clock output of PLL "<name>", uses a cascaded counter, and so it is not fully compensated

CAUSE: The specified output was specified as the compensated output of the PLL. However, it uses cascaded counters, which incur additional delays compared to non-cascaded counters. The additional delay is not fully compensated by the PLL when going through a cascaded counter connection.

ACTION: Change the multiply and/or the divide ratios of the output clock so that cascaded counters are not used, or change the PLL to No Compensation mode if compensation is not required.