ID:10927 In Stratix V engineering sample device, a false EDCRC error on frame 0 occurs after PR completes.

CAUSE: You specified both CRC block and pr block in the design. The Stratix V engineering sample hardware have problem when using PR and EDCRC checking together. Production silicon has fixed the issue.

ACTION: Turn EDCRC off when you have PR for Stratix V engineering sample device. You can turn off the EDCRC by disabling the Enable Error Detection CRC_ERROR pin option.