ID:170089 <text> of routing delay (approximately <text> of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.

CAUSE: This information message indicates the amount of chip-wide wiring resources that are solely used to satisfy hold requirements.

ACTION: Verify that timing constraints, particularly multicycles, are set properly. Avoid using gated clocking. Enabling the Perform Clocking Topology Analysis During Routing setting available in the in the Advanced Fitter Settings dialog, may reduce the amount of delay added to meet hold timing.