ID:10518 VHDL type mismatch error at <location>: <type> type does not match real literal

CAUSE: In a Signal Assignment Statement, Variable Assignment Statement, Subtype Declaration, Type Declaration, or generic Interface List at the specified location in a VHDL Design File (.vhd), you used a real literal for the specified type. However, you cannot use real literals for the specified type. If this error occurs in a generic Interface List, you may have used the real literal as an actual in an Association List for a formal in a VHDL entity or an entity in another source language.

ACTION: Remove the real literal from the assignment, declaration, or Association List, or change the type to one that allows real literals.