ID:10381 VHDL Type Mismatch error at <location>: indexed name returns a value whose type does not match "<type>", the type of the target expression

CAUSE: In a VHDL Design File (.vhd) at the specified location, you indexed an array object and assigned the indexed value to a target expression with the specified type, which does not match the type of the indexed value. In VHDL, you cannot directly assign or associate objects with different types. For example, the Signal Assignment Statement in the following code assigns the expression i(0) to the target my_sig. i was declared with type std_logic_vector, so the indexed name i(0) returns a value with type std_logic, which does not match the type bit declared for my_sig.

ENTITY example IS
   PORT
   (
      i :  IN   std_logic_vector (0 to 3);
      o :  OUT  std_logic_vector (0 to 3)
   );
END example;
 
               
ARCHITECTURE  ex1 OF example IS
   signal my_sig : bit;
BEGIN
   my_sig <= i(0);
END ex1;