ID:10163 Verilog HDL error at <location>: illegal name "<name>" used in expression

CAUSE: In a Verilog Design File (.v) at the specified location, you used a name in an expression, but the name is not legal for use in the expression. For example, this error may occur if you instantiate a module, and then try to assign the instantiated module to another signal, as shown in the following example:

sub sub_inst (in1, in2, temp);  /* instantiate module sub */
assign out = sub_inst;          /* invalid: try to assign sub_inst to out */