ID:14664 SystemVerilog error at <location>: can't resolve unsized bit literal in connection to port <text> on instance "<name>" because the instance has no module binding

CAUSE: The Quartus Prime software could not process a port connection expression with an unsized bit literal because the instantiated module has not been defined. Without the module definition, thecompiler cannot properly extend the bit literal to match the size of the formal port.

ACTION: The module definition cannot be found through automatic discovery. Instead, you must add the module definition to the current revision manually. Alternatively, you can use an extern module declaration, which will be required if you are instantiating a design entity written in a different language such as VHDL.