ID:13672 VHDL error at <location>: illegal <> in expression

CAUSE: In a VHDL Design File (.vhd) at the specified location, you used the undefined range symbol (<>) in an expression. However, the expression must have a defined range. For example, the expression may not be a type, or may be a subtype of a constrained type.

ACTION: Change the undefined range symbol in the expression to a defined range, or change the expression so it can contain the undefined range symbol.