ID:13870 VHDL Binding Indication error at <location>: design entity "<name>" does not contain port "<name>" specified in associated component

CAUSE: In a Binding Indication at the specified location in a VHDL Design File (.vhd), you associated a component with the specified design entity. However, the Component Declaration for the component contains the specified actual port, which does not exist as a formal port in the design entity. The port names and types in the component's Component Declaration must match those in the design entity.

ACTION: Add the port (with the same name and type) to the design entity, or remove the port from the component's Component Declaration.