ID:13375 Unsupported Verilog HDL feature error at <location>: real number in conditional operator (?:) expression is not supported

CAUSE: In a Verilog Design File (.v) at the specified location, you used a real number as the condition to check in a conditional operator (?:) expression. Although Verilog HDL supports real numbers in conditional operator expressions, the Quartus Prime software does not support the use of real numbers in conditional operator expressions.

ACTION: Make sure the conditional operator expression does not contain real numbers.