ID:13368 Verilog HDL Gate Instantiation error at <location>: gate requires <number> inputs and outputs

CAUSE: In a Verilog Design File (.v) at the specified location, you used a Gate Instantiation for a predefined logic gate; however, the logic gate is not using the expected number of input and output ports. The gate requires the specified number of connections to function correctly in the design.

ACTION: Check the port syntax in the Gate Instantiation and adjust the connection list accordingly.