ID:13508 Verilog HDL Module Instantiation error at <location>: cannot connect instance ports both by order and by name

CAUSE: In a Verilog Design File (.v), you instantiated a module and connected its ports using both port connection styles--by order and by name. Verilog HDL does not allow you to mix the two styles; you must connect the ports of an instance entirely by order or entirely by name.

ACTION: Connect instance ports entirely by order or entirely by name.