ID:13493 Verilog HDL Module Instantiation error at <location>: illegal connection to port "<port name>" in array of instances - the actual bit length (<number>) does not equal either the formal port width (<number>) or the product of the formal port width and the number of instances (<number>)

CAUSE: In a Verilog Design File (.v) at the specified location, you connected the specified formal port of an array of instances to an actual with an illegal size. In an array of instances port connection, Verilog HDL hooks up the actual to the formal ports in the array of instances differently depending on three factors: the size of the actual (A), the size of the formal (F), and the number of instances (I). If the actual size matches the formal size, then the full actual is connected to the corresponding formal port of each instance in the array. If the actual size equals the product of the formal size and the number of instances (N), that is, A = F * I, then the actual is sliced into I equal slices of size F; the first slice is connected to the formal port of the first instance in the array, the second slice is connected to the formal port of the second instance, and so on. You received this message because neither case applies to your array of instances. As a result, Quartus Prime Integrated Synthesis cannot determine how to connect the actual to the formal ports in your array of instances.

ACTION: Check the size of the actual, the size of the formal, and the number of instances. Change one or more of these so that the actual size equals either the formal size or the product of the formal size and the number of instances.