ID:13572 SystemVerilog typedef error at <location>: reference to type "<string>" creates a recursive type

CAUSE: In a typedef at the specified location in a Verilog Design File(.v), you declared a user-defined type based on the specified type. However, the specified type itself depends directly or indirectly on the user-defined type you are declaring. Thus, you have a sequence of one or more typedefs that create a circular type dependency. For example, in the following code fragment, the three typdefs create a circular type:

typedef A B;
typedef B C;
typedef C A;