ID:11574 ATX PLL node "<name>" uses an output frequency of <name> MHz that exceeds the maximum frequency of <name> MHz in the targeted speed grade "<name>" for a <name> ATX PLL in a transceiver bank.

CAUSE: The Auxiliary Transmit Phase-Locked Loop (ATX PLL) output frequency exceeds the maximum frequency of the placed location.

ACTION: Refer to the Stratix V Errata document to determine the correct speed grade and PLL location for the ATX PLL to support the desired output frequency.