ID:12260 There are <number> CDR PLLs under reference clocks: <text> , which exceeds the capacity of <number> PLLs provided by the HSSI channel. Modify the design to ensure CDR PLLs driven by the reference clock set is less than the number of CDR PLLs supported for the target device.

CAUSE: The number of CDR PLLs feeding the specified reference clocks exceed the specified device capacity of CDR PLLs.

ACTION: Modify the design to ensure CDR PLLs driven by the reference clock set is less than the number of CDR PLLs supported for the target device.