ID:20080 The second pipeline register of dynamic control input "<parameter value>" of the DSP block WYSIWYG primitive "<name>" is enabled without having second pipeline register enabled or it is using different clock enable source as the second pipeline register.

CAUSE: The specified DSP block WYSIWYG primitive input pipeline register of dynamic control signal can only be enabled when second pipeline register is enabled. Also, when they are enabled, both must share the same clock enable source.

ACTION: Change your design such that the dynamic input second pipeline register and second pipeline register are enabled and both are using the same clock enable source.