Input Delay from Pin to Input Register logic option

A logic option that specifies the propagation delay from an input pin to the data input of the input register implemented in the I/O cell associated with the pin. Use this advanced option after you compile a project, check the I/O timing, and determine that the timing is unsatisfactory. For detailed information on how to use this option, refer to the data sheet for the device family.

This option is useful for fine-tuning the I/O timing of your design and meeting tSU and tH requirements.

This option is ignored if it is applied to anything other than an input or bidirectional pin. This option is available for supported device (Arria^® II GX, Cyclone^® III, and Cyclone^® IV) families.