generate_project_ip_files (::quartus::ipgen)
The following table displays information for the generate_project_ip_files Tcl command:
Tcl Package and Version |
Belongs to ::quartus::ipgen 1.0 |
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Syntax | generate_project_ip_files [-h | -help] [-long_help] [-clean] [-clear_ip_generation_dirs] [-simulation <verilog|vhdl> ] [-synthesis <verilog|vhdl> ] | |||
Arguments | -h | -help | Short help | ||
-long_help | Long help with examples and possible return values | |||
-clean | Specify whether pre-existing generation directories should be cleared before generation. | |||
-clear_ip_generation_dirs | Specify whether pre-existing generation directories should be cleared before generation. | |||
-simulation <verilog|vhdl> | Set the simulation target type. Valid values are verilog or vhdl. | |||
-synthesis <verilog|vhdl> | Set the synthesis target type. Valid values are verilog or vhdl. | |||
Description |
This command generates the files for all Platform Designer IP in the opened project. If no option is specified, this command generates the verilog synthesis target only. --synthesis <value>: Specify the synthesis target type. Valid values are verilog or vhdl. This is not a required option. When not specified, it defaults to verilog. --simulation <value>: Specify the simulation target type. Valid values are verilog or vhdl. This is not a required option. When not specified, no simulation files are generated. --clear_ip_generation_dirs: Specify whether pre-existing generation directories should be cleared before generation. This is not a required option. When not specified, the generation directories will not be cleared. --clean: Specify whether pre-existing generation directories should be cleared before generation. This option is a short version of the clear_ip_generation_dirs option. This is not a required option. When not specified, the generation directories will not be cleared. |
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Example Usage |
# generate all the Platform Designer IP in the project with the specified targets. Clear any pre-existing # generation directories before performing the generation. project_open my_project generate_project_ip_files -synthesis=verilog -simulation=verilog -clear_ip_generation_dirs |
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Return Value | Code Name | Code | String Return | |
TCL_OK | 0 | INFO: Operation successful | ||
TCL_ERROR | 1 | ERROR: The file <string> does not exist in project. | ||
TCL_ERROR | 1 | ERROR: You must open a project before you can use this command. | ||
TCL_ERROR | 1 | ERROR: The command failed with an unknown error. |