HyperFlex Settings

The HyperFlex settings page controls whether Fast Forward Compilation analyzes and reports results for specific logical structures in the Intel® Hyperflex™ architecture of the Intel® Stratix® 10 FPGA. You access this page by clicking AssignmentsSettingsHyperFlex. Turn on Run Fast Forward Timing Closure Recommendations during compilation to enable Fast Forward analysis during the compilation flow by default. To access the following additional settings, click Advanced Settings.
Table 1. Advanced HyperFlex Settings
Option Description
Fast Forward Compile Asynchronous Clears Specifies how Fast Forward analysis accounts for registers with asynchronous clear signals. The options are:
  • Auto—the Compiler identifies asynchronous clears as asynchronous until they limit timing performance during Fast Forward Compilation, at which point the Compiler identifies the asynchronous clears as removed.
  • Preserve—the Compiler never assumes removal or conversion of asynchronous clears for Fast Forward analysis.
Fast Forward Compile Cut All Clock Transfers Cuts all clock transfers in Fast Forward Compilation analysis.
Fast Forward Compile Fully Registered DSP Blocks Specifies how Fast Forward analysis accounts for DSP blocks that limit performance. Enable this option to generate results as if all DSP blocks are fully registered.
Fast Forward Compile Fully Registered RAM Blocks Specifies how Fast Forward analysis accounts for RAM blocks that limit performance. Enable this option to analyze the blocks as fully registered.
Fast Forward Compile Maximum Additional Pipeline Stages Specifies the maximum number of pipeline stages that Fast Forward compilation explores.
Fast Forward Compile User Preserve Directives Specifies how Fast Forward compilation accounts for restrictions from user-preserve directives.