Cyclone® V Device Family Definition

An Intel device family that is a cost-effective solution for data path applications. The Cyclone® V device family includes Cyclone® V E, Cyclone® V GX, Cyclone® V GT, and Cyclone® V SoC devices. The Cyclone® V device architecture supports M10K and MLAB memory blocks to implement single-port, dual-port, and true dual-port memory, and high-speed interfaces to external memory devices such as double data rate type two (DDR2), and double data rate type three (DDR3) synchronous dynamic random access memory (SDRAM). CycloneV devices also contain embedded multiplier blocks that enable efficient implementation of high-performance filters and multipliers.

Cyclone® V E devices are optimized for the lowest system cost and power requirement for a wide spectrum of general logic and digital signal processing (DSP) applications.

Cyclone® V GX devices are optimized for the lowest cost and power requirement for 614-megabits per second (Mbps) to 3.125-gigabits per second (Gbps) transceiver applications.

Cyclone® V GT are low-cost and low-power devices for 5-Gbps transceiver applications.

Cyclone® V SOC devices feature a hard processor system (HPS) block that consists of a dual-core ARM Cortex-A9 MPCore processor, peripherals, shared multiport memory controller, and an FPGA integrated into a single device.

Cyclone® V devices provide up to eight fractional PLLs per device, which provide advanced multiplication, programmable duty cycle, phase shifting, programmable bandwidth, manual clock switchover, clock outputs driving all networks, and normal and zero delay buffer modes. Cyclone® V devices also provide up to 16 global clock networks at up to 550 MHz that drive the global clock network throughout the entire device.

Cyclone® V devices support numerous single-ended and differential I/O standards.

The memory blocks of a Cyclone® V device can implement shift registers and various types of memory with or without parity bits, including dual-port, true dual-port RAM, and single-port RAM; ROM; FIFO buffers; and filter delay lines.

Note: For more information aboutArria® V FPGAs, refer to the webcasts and videos on the Altera website.