To perform a gate-level functional simulation of a Verilog HDL design with the IES GUI

  1. If you have not already done so, set up the IES working environment.
  2. To start the IES software, type nclaunch at a command prompt.
  3. Click File > Set Design Directory.
  4. Browse to your design directory.
  5. Click Create cds.lib File. In the New cds.lib File dialog box, select the libraries to include and click Save.
  6. Under Work Library, click New.
    Note: Intel recommends using the IES (Verilog or VHDL) default library names when you create a library. You should name the IES software libraries as follows:
    • When you run the IES software independently from the Intel® Quartus® Prime software, you should name your library work.
    • When you run the IES software automatically from the Intel® Quartus® Prime software to perform a gate-level simulation, your library is automatically named gate_work under the current project directory, and the work alias is mapped to the gate_work directory.
  7. Specify your new work library name; for example, type work.
  8. Click OK.
  9. Repeat steps 7 and 8 for each functional simulation library; for example, for other work library names, you could type lpm, altera_mf, altera.
  10. In the Set Design Directory dialog box, click OK.
  11. If not already done, on the Edit menu, click Setup File Types, and add *.vo and *.svo as NCVlog file types, and *.vho as the NCVhdl file type.
  12. In the Library Browser, right-click the files you want to compile, and then click NCVlogon the pop-up menu.
  13. In the Compile Verilog dialog box, you will see a list of all of the files you selected. Apply any wanted options, and then click OK.