Global and Other Fast Signals Details Report

Lists the results for the Name, Source Type, Source Location, Fan-Out, Clock Region, Clock Region Size, Spine Used, Path Length from Clock Source to Clock Tree, Clock Tree Depth, Clock Enable Gate Type, and Enable Signal for your design.
  • Name—The source of the clock signal.
  • Source Type
  • Source Location—Location where the source is placed.
  • Fan-Out—Number of input terms driven by the signal across the clock network.
  • Promotion Reason—Displays the reason a given signal was promoted. Results include:
    • Promoted due to design settings—Selected when the design constrains a signal, for example by assignment or clock IP.
    • Standard promotion candidate—Selected for signals that the compiler judges as eligible for promotion. You can override this in the .qsf file.
    • Standard promotion candidate (required due to hardware constraints)—Selected for signals promoted because the hardware requires these signals to use the global network.
    • Promoted automatically by compiler— signals automatically promoted by the compiler because that seems the best choice for quality of results
  • Clock Region—Represents a clock region being driven by the signal. If the signal only drives a single sector the report shows the sector, for example: Sector (2,4). If the signal drives a clock region containing more than one sector the report shows the bottom-left and top-right sectors, for example: Sectors (3,4) to (7,8).
  • Clock Region Size—Shows the dimensions of the clock region in units of sectors and the total number of sectors in that region, for example: 5 x 5 (25 total).
  • Spine Index used in each Sector—Shows the clock spine(plane) at which the clock tree terminates.
  • Path Length from Clock Source to Clock Tree—Shows the length of the path in the clock network from the source of the clock to the root of the clock tree. The length is displayed in terms of the number of sector wires or seams.
  • Clock Tree Depth—Shows the length of the path from the root of the clock tree to the sectors being driven in terms number of sector wires or seams.
  • Clock Enable Gate Type—This row is only shown if the clock signal is using a clock gate and displays the enable type being used, either Root or Sector.
  • Enable Signal—This row is only shown if the clock signal is using a clock gate and displays the name of the enable signal feeding the clock gate.