Virtual Pin logic option

Specifies whether an I/O element in a lower-level design entity can be temporarily mapped to a logic element and not to a pin during compilation. The virtual pin is then implemented as a LUT. This option should be specified only for I/O elements that become nodes when imported to the top-level design.

This option is useful when compiling a Logic Lock module with more pins than the current device allows. Turning on this option provides timing analysis that can more closely match the performance of the Logic Lock module when it is integrated into the top-level design.

This option must be assigned to an input or output pin or it is ignored. If you assign this option to a bidirectional pin, tri-state pin, or registered I/O element, Analysis and Synthesis ignores this assignment. If you assign this option to a tri-state pin the Fitter inserts an I/O buffer to account for the tri-state logic, therefore the pin cannot be a virtual pin. You can use multiplexer logic instead of a tri-state pin if you want to continue to use the assigned pin as a virtual pin. Do not use tri-state logic except for signals that connect directly to device I/O pins.

This option is available for all Intel devices supported by the Intel® Quartus® Prime Pro Edition software.

Scripting Information

Keyword: virtual_pin

Settings: on | off*

*default