Virtual Pin Clock logic option

A logic option that specifies the name of the clock to be used for the I/O element specified with the Virtual Pin logic option. During compilation, virtual pins are implemented as LUTs. You can use the Virtual Pin Clock option to make clock assignments to the virtual pins, allowing you to analyze the timing as part of the correct clock domain.

The clock used for the virtual pin can be a pin or an internal node. If you turn on the Virtual Pin logic option but do not specify a clock with the Virtual Pin Clock logic option or the clock you specified does not exist, the Compiler finds a clock by traversing the fan-in and fan-out of the I/O element. If there are no clocks in the fan-in and fan-out of the I/O element, the Compiler assigns the clock to GND. During compilation, virtual pins are implemented as registers.

If the current design has stringent timing requirements, make sure:

  • The Virtual Pin Clock logic option is assigned specific clocks.
  • The virtual pins are placed into a small Logic Lock region. If the Compiler is able to meet timing requirements on this path, the timing results can be preserved when the region is exported into a higher-level design.

If the current design does not have stringent timing requirements and you did not assign specific clocks with the Virtual Pin Clock logic option, the Compiler may issue warnings that timing requirements were not met. Timing violations in virtual pin paths may be ignored because these registers represent simple input or output pins and the registers will be converted back to pins or ports in the highest level of the design hierarchy.

This option must be assigned to either an input pin or an output pin or it is ignored.

This option is available for supported device (MAX® II, and MAX® V) families.

Scripting Information

Keyword: use_clk_for_virtual_pin

Settings: <clock name>