D6 Delay (output register to I/O buffer) logic option

A logic option that specifies the propagation delay from the I/O buffer to the output pins for the D6 delay cell. This is an advanced option; use this option only after compiling your project, checking I/O timing, and determining that timing is unsatisfactory. This option is ignored if it is applied to anything other than an input or bidirectional pin.

This option is available for supported device (Arria® II GZ, Stratix® III, Stratix® IV, and Stratix® V) families.

Scripting Information

Keyword: d6_delay

Settings:<integer>

Note:

For more information, refer to the data sheet for the relevant device family, which is available from the Literature section of the Altera website.