Router Timing Optimization Level logic option

Specifies the amount of effort the router spends trying to optimize the timing requirements of your design.

This option is useful if you want to control the amount of compilation time spent in the router.

This is a project-wide option. This option is available for supported device (Arria^® series, Cyclone^® series, MAX^® II, MAX^® V, and Stratix^® series) families.