Restructure Multiplexers logic option

A logic option that allows the Compiler to reduce the number of logic elements required to implement multiplexers in a design. This option is useful if your design contains buses of fragmented multiplexers. This option repacks multiplexers more efficiently for area, allowing the design to implement multiplexers with a reduced number of logic elements.

The Restructure Multiplexers option works on entire trees of multiplexers. Multiplexers may arise in different parts of the design through VHDL or Verilog constructs such as "if", "case", or "?:". When multiplexers from one part of the design feed multiplexers in another part of the design, trees of multiplexers are formed. The Restructure Multiplexers option identifies buses of multiplexer trees that have a similar structure. Multiplexer buses occur most often as a result of multiplexing together vectors in Verilog, or array types such as STD_LOGIC_VECTOR in VHDL. When turned on, the Restructure Multiplexers option optimizes the structure of each multiplexer bus for the target device to reduce the overall number of logic elements used in the design. Once you have compiled your design, you can view multiplexer restructuring information in the Multiplexer Restructuring Statistics section of the Compilation Report.

This option must be assigned to a design entity or node or it is ignored.

This option is available for all Intel devices supported by the Intel® Quartus® Prime software except MAX3000 and MAX7000 devices..


For more information about using multiplexer restructuring in the Intel® Quartus® Prime software, see the "Recommended HDL Coding Styles" chapter in volume 1 of the Intel® Quartus® Prime Handbook, which is available from the Literature section of the Altera website.

Scripting Information

Keyword: mux_restructure

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