HDL Initial Fan-out Limit logic option

Directs Analysis & Synthesis to issue a warning if a net in the post-elaboration netlist exceeds the specified limit. The post-elaboration netlist is the initial netlist created by elaborating a single entity in your HDL source. It is possible that the later synthesis and fitter optimizations may reduce (or increase) the fan-out of the nets in the netlist. This option is useful for identifying high-fanout signals early in the design process.

This option is ignored if applied to anything other than an entity or an instance of an entity. This option is available for all Intel devices.

Scripting Information


Settings: <fanout limit> -to <entity name>