Force Use of Synchronous Clear Signals logic option

A logic option that forces the compiler to utilize synchronous clear signals in normal mode logic cells. Turning this option on helps to reduce the total number of logic cells used in the design, but may negatively impact the fitting since synchronous control signals are shared by all logic cells in a Logic Array Block (LAB) Definition

This option is available for all Intel devices supported by the Intel® Quartus® Prime software.

Scripting Information

Keyword: force_synch_clear

Settings: on | off

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