DQSn/DQS Pair logic option

A logic option that specifies the pairing of a DQSn pin to a DQS pin. The I/O pin of a DQS must be placed in the DQS pin location of a DQS group; the I/O pin of a DQSn must be placed in the DQSn pin location of the same DQS group.

This option must be assigned to an I/O pad, input buffer, or output buffer or it is ignored.

This option is available for supported device (Arria^® II, Cyclone^® III, Cyclone^® IV, Stratix^® III, and Stratix^® IV) families.