Synchronizer Identification logic option

A logic option that specifies how the Timing Analyzer identifies registers as being part of a synchronization register chain for metastability analysis. A synchronization register chain is a sequence of registers with the same clock with no fan-out in between, which is driven by a pin or logic from another clock domain. You can choose one of the following settings:

Setting

Description

Off

The Timing Analyzer does not identify the specified registers, or the registers within the specified entity, as synchronization registers.

Note: Off cannot be used as a global assignment.

Auto

The Timing Analyzer identifies valid synchronization registers that are part of a chain with more than one register that contains no combinational logic.

Note: MTBF is not reported for automatically-detected register chains.

Forced if Asynchronous

The Timing Analyzer identifies synchronization register chains if the software detects an asynchronous signal transfer, even if there is combinational logic or only one register in the chain.

Forced

The specified register, or all registers within the specified entity, are identified as synchronizers.

Important: Important: The Forced option should not be applied to the entire design, because doing so identifies all registers in the design as synchronizers.

Registers that are identified as synchronizers are optimized for improved Mean Time Between Failure (MTBF) as long as the Optimize Design for Metastability option is turned on. If a synchronization register chain is identified with the Forced or Forced If Asynchronous option, then the Timing Analyzer reports the metastability MTBF for the chain. MTBF is not reported for automatically-detected register chains; you can use the Auto setting to generate a report of possible synchronization chains in your design. If a synchronization register chain is identified with the Forced or Forced if Asynchronous option, then the Timing Analyzer reports the metastability MTBF for the chain when it meets the design timing requirements.

This option is available for all Intel devices supported by the Intel® Quartus® Prime software except MAX® II, MAX3000, and MAX7000 devices families.

Scripting Information

Keyword:synchronizer_identification

Settings: off | auto* | "forced if asynchronous" | forced

*default

Note: For more information about metastability, see the "Managing Metastability with the Intel® Quartus® Prime Software" chapter in the Intel® Quartus® Prime Handbook, volume 1.