Shift Register Replacement - Allow Asynchronous Clear Signal logic option

Allows the Compiler to replace shift registers that use the asynchronous clear signal with the altshift_taps Intel® FPGA IP.

This option can be used as a project-wide option, or assigned to a design entity. This option is available for all Intel devices supported by the Intel® Quartus® Prime software.

Scripting Information

Keyword: shift_register_recognition_aclr_signal

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