direct_enable Verilog HDL Synthesis Attribute

A Verilog HDL synthesis attribute that guides Intel^® Quartus^® Prime Integrated Synthesis as to which signals it should prefer as clock enable signals to the registers. Using this attribute prevents Intel^® Quartus^® Prime Integrated Synthesis from synthesizing a different clock enable from the one that you prefer to use.

Note: Analysis & Synthesis also recognizes the synonymous synthesis attribute syn_direct_enable. This synthesis attribute behaves identically to the direct_enable synthesis attribute.

In the example code below, Intel^® Quartus^® Prime Integrated Synthesis would normally create a clock enable equation for the registers that would include both signals ce0 and ce1. However, with the direct_enable attribute set to ce1, ce1 is the clock enable signal and ce0 is part of the logic feeding the data input of the registers.

module top (d, clock, ce0, ce1, q);
 input [31:0] d;
 input clock;
 input ce0;
 (* direct_enable = 1 *) input ce1;
 output reg [31:0] q;  always @ (posedge clock)
 begin
  if (ce1)
  begin
   if (ce0)
   begin
    q <= d;
   end
  
end
 
end
endmodule

You can also use this attribute to prevent Intel^® Quartus^® Prime Integrated Synthesis from "unmapping" a clock enable signal, that is, synthesizing the clock enable signal back into the data input of the register. Intel^® Quartus^® Prime Integrated Synthesis sometimes unmaps clock enable signals that qualify as underutilized. If you want a specific signal to be the clock enable signal, setting this attribute prevents Intel^® Quartus^® Prime Integrated Synthesis from unmapping the clock enable signal.