translate_off and translate_on VHDL Synthesis Directives

VHDL synthesis directives that direct Analysis & Synthesis to ignore portions of the design code that are specific to simulation and not relevant to logic synthesis.

To use the translate_off and translate_on synthesis directives, you can specify the translate_off synthesis directive in a comment located immediately before the code you want Analysis & Synthesis to ignore, and specify the translate_on synthesis directive in a comment located immediately after the code you want Analysis & Synthesis to ignore. In the comment, precede the synthesis directive with the synthesis keyword. The text between the directives is treated as if each line is preceded by a single-line comment delimiter. Syntax checking is not performed and there is no requirement that the text be valid VHDL.

For example, in the following code, Analysis & Synthesis ignores the code USE std.textio.all;, and performs logic synthesis on any code after the comment -- synthesis translate_on (unless the user uses the translate_off and translate_on synthesis directives again):

You can use the Ignore translate_off and translate_on Synthesis Directives logic option to disable all translate_off and translate_on synthesis directives in a design, allowing you to use the sections previously ignored during a compilation.