Verilog HDL Example Instantiation

//myddio_bidir is an instance of the altddio_bidir Intel® FPGA IP
        myddio_bidir sample_ddio (     .aset(aset),
                                       .combout(combout),
                                       .datain_h (datain_h),
                                       .datain_l(datain_l),
                                       .inclock(inclock),
                                       .oe(oe),
                                       .outclock(outclock),
                                       .padio(tmp_padio),
                                       .oe_out(tmp_oe),
                                       .sclr(sclr)
                                 );
alt_bidir_buf my_bidir (.bidirin (tmp_padio), .oe (tmp_oe), .io (bidir)); //Here, ”r;bidir” should be declared as an inout port.