altsquare Intel FPGA IP

Parent topic: altsquare Intel FPGA IP

Output Ports

Port Name	Required	Description	Comments
`result[]`	Yes	This port is set to `[data * data]`.	Output port with width `[RESULT_WIDTH-1..0]`.

Parent topic: altsquare Intel FPGA IP

Contact Intel | Terms of Use | Trademarks | Privacy | Send Feedback

Copyright© Intel Corporation. All rights reserved. INTEL, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Intel Corporation in the U.S. and other countries.