Performing Gate-Level Functional Simulation of a Verilog HDL Design with the Active-HDL Software

You can run the Aldec Active-HDL software to perform gate-level functional simulation of a Verilog HDL design that contains Intel-specific components from the Active-HDL interface. You can use simulation libraries provided with the Intel^® Quartus^® Prime software, or download simulation libraries directly from Aldec.

Note: For more information about using EDA simulators, refer to Aldec Active-HDL and Riviera-PRO Support in the Intel^® Quartus^® Prime Handbook.