Start Fitter Commands (Processing Menu)

You can access these commands by clicking Processing > Start > Start Fitter.

The Fitter places and routes the logic of your synthesized design into target device resources. Click Processing > Start Fitter to run all stages of the Fitter. Use the incremental optimization flow to run and optimize individual Fitter stages before running the other Fitter stages. Click any of the following commands to run individual Fitter stages:

Table 1. Fitter Stage Commands



Fitter (Implement) Runs the Plan, Early Place, Place, Route and Retime stages. Click the adjacent Timing Analyzer icon after this stage to analyze the subset of timing corners needed for timing closure.

Start Fitter (Plan)

Loads synthesized periphery placement data and constraints, and assigns periphery elements to device I/O resources. After this stage, you can run post-Plan timing analysis to verify timing constraints, and validate cross-clock timing windows. View the placement and properties of periphery (I/O) and perform clock planning for Intel® Arria® 10 and Intel® Cyclone® 10 designs. This command creates the planned snapshot.

Start Fitter (Early Place)

Places all core elements in an approximate location to facilitate design planning. After this stage, the Chip Planner displays initial high-level placement of design elements. The Compilation reports identifies high fan-out signals that increase placement complexity. Use this information to guide your floorplanning decisions. For Intel® Stratix® 10 designs, you can also do early clock planning after this stage. This command creates the early placed snapshot. Early Place does not run during the full compilation flow.

Start Fitter (Place)

Places all core elements in a legal location. This command creates the placed snapshot.

Start Fitter (Route)

Creates all routing between the elements in the design. After this stage, validate delay chain settings and analyze routing resources. Perform detailed setup and hold timing closure in the Timing Analyzer and view routing congestion via the Chip Planner. This command creates the routed snapshot.

Start Fitter (Retime)

Performs register retiming and moves existing registers into Hyper-Registers to increase performance by removing retiming restrictions and eliminating critical paths. The Compiler may report hold violations for short paths following the Retime stage. The Fitter identifies and corrects the short paths with hold violations during the Fitter (Finalize) stage by adding routing wire along the paths. This command creates the retimed snapshot.

Start Fitter (Finalize)

Performs post-routing optimization on the design. This stage converts unneeded tiles from High Speed to Low Power. This command creates the final snapshot. For Intel® Stratix® 10 designs, the Fitter also runs post-route fix-up to correct any short path hold violations remaining from retiming.

Note: During Analysis & Synthesis, you can click the Concurrent Analysis icons on the Dashboard to view reports, the RTL Viewer, or the Technology Map Viewer. While the Fitter is processing, you can analyze timing during the stages displaying the Timing Analyzer icon, and view Technology Map Viewer snapshots during Fitter stages. You cannot modify timing constraints during concurrent analysis. However, you can stop compilation processing at any time, modify your .sdc constraints, and then click the Timing Analyzer icon to analyze the design with the modified constraints.