Create Generated Clock Dialog Box (create_generated_clock)

You access this dialog box by clicking Constraints > Create Generated Clock in the Timing Analyzer, or with the create_generated_clock Synopsys® Design Constraints (SDC) command.

Allows you to define the properties and constraints of an internally generated clock in the design. You specify the clock name (-name), the source node (-source) from which the generated clock is derived, the relational properties to the source clock, and the target signals to which the constraints apply.

The following sections provide more information about specifying options for this constraint:

Clock Name:

Allows you to specify a unique name for the clock. If you do not specify a name in the Clock name box (-name), the Timing Analyzer uses the first name specified in the Targets box.

Source:

Specifies the source (-source) of the generated clock. The source must be a pin or port in the design. All waveform properties of the generated clock are relative to the source. If more than one clock signal feeds the source node, you must use the command-line interface to set the - master_clock option to specify from which clock the generated clock is derived. The source latency of the generated clock is based on its own clock network, and not the clock network of the source node. This latency is added to any source latency of the master clock. You can use the Name Finder (...) to specify a source.

Based on frequency:

Allows you to define the relationship of the generated clock relative to the frequency of the master clock. The following options are available:

  • Divide by (-divide_by)— Specifies that the frequency of the generated clock is a fraction of the frequency of the master clock. The clock division is performed relative to the first rising edge. Clock division is based on the edges of the master clock waveform, and scaled if the division is an odd number.
  • Multiply by (-multiply_by)— Specifies that the frequency of the generated clock is a multiple of the frequency of the master clock. The clock multiplication is performed relative to the first rising edge. Clock multiplication is based on the edges in the master clock waveform.
  • Duty cycle (-duty_cycle)— Specifies the new duty cycle for clock multiplication or division.
  • Phase (-phase)— Specifies any phase shift relative to the new clock period.
  • Offset (-offset)— Specifies an arbitrary offset or time shift.
Note: You can specify a basic clock divider equivalently with -divide_by 2 or -edges {1 3 5}.

Based on waveform:

Allows you to specify the relationship of a generated clock relative to the base clock edges (-edges) and edge shifts (-edge_shift). Master clock edges are labeled starting with the first rising edge, next falling edge, and next rising edge in the Edge list boxes. You can specify the edge shift values in the in the Edge shift list boxes.

Note:
  • In the Edge list boxes, you can specify values in the default time unit, or in a different time unit by entering the value and the time unit abbreviation. For example, 300ps.
  • You can specify a basic clock divider equivalently with -divide_by 2 or -edges {1 3 5}.

Invert waveform:

Inverts the waveform from the base clock.

Targets:

Allows you to specify the targets to which the constraint applies. If the specified target already has a clock definition, the Timing Analyzer overwrites the original clock definition for that target unless you use the -add option. You can use the -add option to assign multiple clocks to a pin or port. If the constrained clock is on a path following another clock, then the Create Generated Clock constraint blocks or overwrites the previous clock from the point where the generated clock is assigned to the targets. If you do not specify a target, the generated clock acts as a virtual clock. You can use the Name Finder (...) to build a collection Definition of targets.

SDC Command:

Displays and allows you to enter SDC commands for the options you specify in this dialog box.