derive_clock_uncertainty (::quartus::sdc_ext)

The following table displays information for the derive_clock_uncertainty Tcl command:

Tcl Package and Version

Belongs to ::quartus::sdc_ext 1.0

Syntax derive_clock_uncertainty [-h | -help] [-long_help] [-add] [-overwrite]
Arguments -h | -help Short help
-long_help Long help with examples and possible return values
-add Adds results user-defined clock uncertainty assignments
-overwrite Overwrites user-defined clock uncertainty assignments
Applies inter-clock, intra-clock and I/O interface uncertainties based
on timing model characterization. This command calculates and applies
setup and hold clock uncertainties for each clock-to-clock transfer
found in the design. The calculation of the uncertainties is delayed
until the next update_timing_netlist call.

To get I/O interface uncertainty in addition to inter-clock and
intra-clock uncertainties, create a virtual clock to represent an
off-chip clock for input or output delay specification and assign
delays to input/output ports with set_input_delay and set_output_delay
commands that specify the virtual clock.

If set_input_delay and set_output_delay commands specifying a non-
virtual clock are called, derive_clock_uncertainty applies either
inter-clock or intra-clock uncertainty for that clock transfer since
those transfers represent a clock-to-clock domain rather than an
I/O-to-register clock domain.

These uncertainties are applied in addition to any previous
set_clock_uncertainty calls. However, if there is already a clock
uncertainty assignment for a source clock and destination clock pair,
the new one is ignored. Either use the -overwrite option to overwrite
previous clock uncertainty assignments or manually remove them by
using remove_clock_uncertainty command. Use the -add option to add the
previous user-defined clock uncertainty values to the derived ones.

This command auto-generates a file named PLLJ_PLLSPE_INFO.txt (or
PLLJ_PLLSPE_INFO_M.txt if a military temperature range is selected)
that lists the names of the PLLs in the design as well as their jitter
and SPE values. This text file can be used by HCII_DTW_CU_Calculator.
Example Usage
# create a virtual clock
create_clock -name virtual -period 1

# apply input/output delays with the virtual clock to get
# I/O interface uncertainties
set_input_delay -clock virtual -add_delay 0 [all_inputs]
set_output_delay -clock virtual -add_delay 0 [all_outputs]

# call derive_clock_uncertainty. results will be calculated 
# at the next update_timing_netlist call

Return Value Code Name Code String Return
TCL_OK 0 INFO: Operation successful