make_sp (::quartus::chip_planner)
The following table displays information for the make_sp Tcl command:
Tcl Package and Version |
Belongs to ::quartus::chip_planner 2.0 |
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Syntax | make_sp [-h | -help] [-long_help] [-clk <clock signal name> ] [-io_std <io standard> ] -loc <location> -pin_name <pin name> [-regs <num> ] [-reset <reset signal name> ] -src_name <source name> | |||
Arguments | -h | -help | Short help | ||
-long_help | Long help with examples and possible return values | |||
-clk <clock signal name> | Clock signal for the register in the Signal Probe pipeline | |||
-io_std <io standard> | I/O standard of the Signal Probe pin | |||
-loc <location> | Pin location of the Signal Probe pin | |||
-pin_name <pin name> | Signal Probe pin name | |||
-regs <num> | Number of pipeline stages for the Signal Probe pin | |||
-reset <reset signal name> | Reset signal for the register in the Signal Probe pipeline | |||
-src_name <source name> | Name of the signal to probe | |||
Description |
Creates a Signal Probe pin connected to the source signal using the specified number of registers. Columns are: Pin_name, pin_lcation, io_standard, oterm_name, number of registers, clock name, reset_name, is enabled, and has ECO changes. |
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Example Usage |
make_sp |
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Return Value | Code Name | Code | String Return | |
TCL_OK | 0 | INFO: Operation successful | ||
TCL_ERROR | 1 | ERROR: Unable to find Chip Planner netlist. Read the netlist by using the read_netlist command. |