Verilog HDL Example Instantiation

module test_simple (in1,in2,out,outn);
input in1;
input in2;
output out;
output outn;
wire buffer_in;
and(buffer_in, in1, in2);
alt_outbuf_diff inst( .i(buffer_in), .o(out), .obar(outn));
defparam inst.io_standard = "differential 1.5-V SSTL Class I";
defparam inst.current_strength = "4mA";
defparam inst.enable_bus_hold = "off";
endmodule